FIG. 1 depicts a configuration example of a memory device. Each of a first redundant memory 101a, a second redundant memory 101b, and a third redundant memory 101c includes a plurality of normal memory cell blocks and a redundant memory cell block. Even if one of the plurality of normal memory cell blocks includes a defective memory cell, the normal memory cell block including the defective memory cell can be switched to the redundant memory cell block to repair the defective memory cell, and the production yield can be improved. Each of a first flip-flop group 102a, a second flip-flop group 102b, and a third flip-flop group 102c, which are connected to each other in series, includes, for example, four flip-flops. A fuse circuit 105 is a non-volatile memory that stores repair data 103a of the first redundant memory 101a, repair data 103b of the second redundant memory 101b, and repair data 103c of the third redundant memory 101c. The repair data 103b indicates “0000” which denotes that the normal memory cell block is not to be switched to the redundant memory cell block. The repair data 103a and 103b is data other than “0000”, indicating which one of the plurality of normal memory cell blocks is to be switched to the redundant memory cell block.
A data transfer control circuit 104 serially outputs the repair data 103c, 103b, and 103a stored in the fuse circuit 105 to serial connection circuits of the flip-flop groups 102a to 102c to serially transfer the repair data 103a to 103c to the flip-flop groups 102a to 102c. As a result, the repair data 103c is stored in the third flip-flop group 102c, the repair data 103b is stored in the second flip-flop group 102b, and the repair data 103a is stored in the first flip-flop group 102a. The first redundant memory 101a switches the normal memory cell block indicated by the repair data 103a stored in the first flip-flop group 102a among the plurality of normal memory cell blocks to the redundant memory cell block. Since the repair data 103b stored in the second flip-flop group 102b indicates “0000”, the second redundant memory 101b does not switch the normal memory cell blocks to the redundant memory cell block. The third redundant memory 101c switches the normal memory cell block indicated by the repair data 103c stored in the third flip-flop group 102c among the plurality of normal memory cell blocks to the redundant memory cell block.
FIG. 2 depicts a configuration example of another memory device (for example, see Japanese Laid-open Patent Publication No. 2007-193879). Differences between the memory device of FIG. 2 and the memory device of FIG. 1 will be described. The first redundant memory 101a and the third redundant memory 101c include defective memory cells, and the second redundant memory 101b does not include a defective memory cell. The fuse circuit 105 stores: an ID (identifier) 201a and the repair data 103a of the first redundant memory 101a that includes the defective memory cell; and an ID 201c and the repair data 103c of the third redundant memory 101c that includes the defective memory cell. Since the ID 201c of the third redundant memory 101c is stored in the fuse circuit 105, the data transfer control circuit 104 serially transfers the repair data 103c of the third redundant memory 101c to the third flip-flop group 102c. Since an ID of the second redundant memory 101b is not stored in the fuse circuit 105, the data transfer control circuit 104 serially transfers the repair data 103b with a fixed value “0000” to the second flip-flop group 102c. Since the ID 201a of the first redundant memory 101a is stored in the fuse circuit 105, the data transfer control circuit 104 serially transfers the repair data 103a of the first redundant memory 101a to the first flip-flop group 102a. The repair data 103b of the second redundant memory 101b that does not include a defective memory cell does not have to be stored in the fuse circuit 105. Therefore, the storage capacity of the fuse circuit 105 can be reduced.
FIG. 3 depicts a configuration example of yet another memory device (for example, see Japanese Laid-open Patent Publication No. 2007-193879). Differences between the memory device of FIG. 3 and the memory device of FIG. 2 will be described. The data transfer control circuit 104 transfers, in parallel, the three pieces of repair data 103a to 103c to the three flip-flop groups 102a to 102c. This can reduce the transfer time of the repair data 103a to 103c. However, there is a problem that if the number of redundant memories 101a to 101c increases, the number of parallel connection wires between the data transfer control circuit 104 and the flip-flop groups 102a to 102c increases.
There is a known semiconductor integrated circuit including: a memory macro including a main memory cell array with a plurality of memory cells, a redundant memory array with a plurality of redundant cells, and a redundancy relief mechanism; a relief information analysis circuit including a non-volatile storage element that stores memory identification information for identifying the memory macro; and a relief information transfer circuit that transfers unit relief information, which at least includes the memory identification information and relief information, to the relief information analysis circuit (for example, see Japanese Laid-open Patent Publication No. 2009-43328).
There is a known integrated circuit system including: a plurality of memory devices that can relieve redundancy of a defective section by inputting device relief information which is information indicating a configuration for relieving the redundancy; and a plurality of relief information analysis circuits that receive relief information including identification information of the memory devices and device relief information of the memory devices to analyze the relief information, wherein one relief information analysis circuit corresponds to one memory device, and the relief information analysis circuits are serially connected through a serial transfer path (for example, see Japanese Laid-open Patent Publication No. 2008-226285).
There is a known semiconductor integrated circuit device including: a memory cell array including a plurality of memory cells arranged in an array; a redundant circuit that includes a plurality of auxiliary memory cells and that replaces a defective memory cell in the memory cell array with a specific auxiliary memory cell based on programmed address information; a storage circuit that is for programming the address information and that includes a plurality of non-volatile storage elements; and a transfer circuit that transfers the address information programmed in the storage circuit to the redundant circuit (for example, see Japanese Laid-open Patent Publication No. 2004-133970).    [Patent Literature 1] Japanese Laid-open Patent Publication No. 2007-193879    [Patent Literature 2] Japanese Laid-open Patent Publication No. 2009-43328    [Patent Literature 3] Japanese Laid-open Patent Publication No. 2008-226285    [Patent Literature 4] Japanese Laid-open Patent Publication No. 2004-133970